1. Field
This patent document relates to a memory device.
2. Description of the Related Art
In general, a memory cell of a semiconductor memory device such as Dynamic Random Access Memory (DRAM) includes a transistor serving as a switch and a capacitor for storing a charge that is, data. Depending on whether the capacitor of the memory cell is charged or not, that is, whether the terminal voltage of the capacitor is high or low, the logic level of data may be high that is, logic 1 and low that is, logic 0.
Since data are stored in such a manner that charges are accumulated in the capacitor, no power is consumed in principle. However, due to a leakage current caused by a PN junction of a metal-oxide-semiconductor (MOS) transistor, the initial charge stored in the capacitor may disappear. In this case, the data may be lost. In order to prevent such a data loss, the data stored in the memory cell must be read before the data are lost, and the memory cell must be recharged according to the read information. Such an operation must be periodically repeated in order to retain the data. The process of recharging the memory cell is referred to as a refresh operation.
The refresh operation may be performed whenever a refresh command is received in a memory device which includes a plurality of memory cells, from a memory controller. Considering the data retention time of the memory device, the memory controller may transmit the refresh command to the memory device at each predetermined time. For example, when the data retention time of the memory device is 64 ms and the entire memory cells of the memory device can be refreshed only when the refresh command is received 8,000 times, the memory controller transmits 8,000 refresh commands to the memory device for 64 ms.
Furthermore, when the data retention times of some memory cells included in a memory device do not exceed a prescribed reference time during a test process of the memory device, the memory device is processed as a fail. The memory device processed as a fail must be discarded.
When memory devices including memory cells having data retention times which do not reach the reference time, that is, weak cells, are all processed as fails, the yield of the memory devices inevitably decreases. Furthermore, even a memory device having passed through a test may cause an error when a weak cell occurs due to a posterior cause.
Recently, as the number of memory cells integrated in one chip is increased to tens of millions or more, the possibility that weak cells will occur, increases more and more despite the development of the fabrication process. Unless an accurate test is performed on such weak cells, the reliability of the memory device cannot be secured. Thus, research is being conducted on various schemes and methods for detecting a weak cell.